Towards Error Correction for Computing in Racetrack Memory

TL;DR

This paper introduces CIRM-ECC, a novel error correction technique designed to protect Racetrack Memory-based computing-in-memory systems from faults, leveraging the memory's peripheral circuitry to implement ECC codes.

Contribution

It presents a new ECC method tailored for Racetrack Memory CIM systems, capable of protecting against faults using existing Hamming and BCH codes.

Findings

CIRM-ECC effectively corrects CIM faults in Racetrack Memory.

The approach integrates with existing ECC codes like Hamming and BCH.

Demonstrates improved fault tolerance in Racetrack Memory CIM architectures.

Abstract

Computing-in-memory (CIM) promises to alleviate the Von Neumann bottleneck and accelerate data-intensive applications. Depending on the underlying technology and configuration, CIM enables implementing compute primitives in place, such as multiplication, search operations, and bulk bitwise logic operations. Emerging nonvolatile memory technologies such as spintronic Racetrack memory (RTM) promise not only unprecedented density but also significant parallelism through CIM. However, most CIM designs, including those based on RTM, exhibit high fault rates. Existing error correction codes (ECC) are not homomorphic over bitwise operations such as AND and OR, and hence cannot protect against CIM faults. This paper proposes CIRM-ECC, a technique to protect spintronic RTMs against CIM faults. At the core of CIRM-ECC, we use a recently proposed RTM-based CIM approach and leverage its peripheral circuitry to our implement our novel ECC codes. We show that CIRM-ECC can be applied to single-bit Hamming codes as well as multi-bit BCH codes.