Functional ISS-Driven Verification of Superscalar RISC-V Processors

TL;DR

This paper introduces SupeRFIVe, a verification methodology for superscalar RISC-V processors that uses instruction set simulation to efficiently validate correctness, demonstrated on a dual-issue CPU with benchmark tests.

Contribution

The paper presents a novel verification approach combining instruction set simulation with socket communication for superscalar processor validation.

Findings

Effective verification of a RISC-V dual-issue CPU achieved

Demonstrated scalability with benchmark applications

Improved verification efficiency over traditional methods

Abstract

A time-efficient and comprehensive verification is a fundamental part of the design process for modern computing platforms, and it becomes ever more important and critical to optimize as the latter get ever more complex. SupeRFIVe is a methodology for the functional verification of superscalar processors that leverages an instruction set simulator to validate their correctness according to a simulation-based approach, interfacing a testbench for the design under test with the instruction set simulator by means of socket communication. We demonstrate the effectiveness of the SupeRFIVe methodology by applying it to verify the functional correctness of a RISC-V dual-issue superscalar CPU, leveraging the state-of-the-art RISC-V instruction set simulator Spike and executing a set of benchmark applications from the open literature.