Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic

TL;DR

This paper introduces a novel superconducting circuit synthesis method using xSFQ logic that eliminates clock dependency, significantly reducing circuit resource requirements and improving design automation.

Contribution

It presents a clock-free xSFQ logic-based synthesis approach that reduces Josephson junctions by over 80% without modifying existing tools.

Findings

Over 80% reduction in Josephson junction count

Elimination of clock dependency in superconducting circuits

Compatibility with existing synthesis tools

Abstract

Gate-level clocking, typical in traditional approaches to Single Flux Quantum (SFQ) technology, makes the effective synthesis of superconducting circuits a significant engineering hurdle. This paper addresses this challenge by employing the recently introduced alternating SFQ (xSFQ) logic family. xSFQ leverages dual-rail alternating encoding to eliminate the clock dependency from the superconducting gate semantics. This obviates the need for ad hoc modifications to existing synthesis tools and avoids unnecessary circuit resource overheads, marking a significant advancement in superconducting circuit design automation. Our implementation results demonstrate an average reduction of over 80\% in the Josephson junction count for circuits from the ISCAS85, EPFL, and ISCAS89 benchmark suites.