Configurable Multi-Port Memory Architecture for High-Speed Data Communication

TL;DR

This paper introduces a configurable multi-port memory architecture that enhances data transfer speed and area efficiency for high-speed AI data communication, adaptable to various read/write port configurations.

Contribution

A novel pseudo-quad-port memory architecture allowing flexible port configurations, improving bandwidth and area efficiency over traditional fixed-port solutions.

Findings

Bandwidth increased by 4x

Area efficiency improved by 1.3x and 2x

Designed and analyzed using 65nm CMOS technology

Abstract

Memory management is necessary with the increasing number of multi-connected AI devices and data bandwidth issues. For this purpose, high-speed multi-port memory is used. The traditional multi-port memory solutions are hard-bounded to a fixed number of ports for read or write operations. In this work, we proposed a pseudo-quad-port memory architecture. Here, ports can be configured (1-port, 2-port, 3-port, 4-port) for all possible combinations of read/write operations for the 6T static random access memory (SRAM) memory array, which improves the speed and reduces the bandwidth for data transfer. The proposed architecture improves the bandwidth of data transfer by 4x. The proposed solution provides 1.3x and 2x area efficiency as compared to dual-port 8T and quad-port 12T SRAM. All the design and performance analyses are done using 65nm CMOS technology.