SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning

TL;DR

This paper introduces SCART, a machine learning-based model that predicts optimal STT-RAM cache retention times to reduce latency and energy consumption, addressing the challenge of diverse application requirements.

Contribution

The paper presents a novel SCART model that uses SRAM statistics to predict STT-RAM retention times, enabling efficient design and runtime optimization.

Findings

SCART reduces latency by 20.34%

SCART reduces energy consumption by 29.12%

SCART cuts exploration overheads by 52.58%

Abstract

Prior studies have shown that the retention time of the non-volatile spin-transfer torque RAM (STT-RAM) can be relaxed in order to reduce STT-RAM's write energy and latency. However, since different applications may require different retention times, STT-RAM retention times must be critically explored to satisfy various applications' needs. This process can be challenging due to exploration overhead, and exacerbated by the fact that STT-RAM caches are emerging and are not readily available for design time exploration. This paper explores using known and easily obtainable statistics (e.g., SRAM statistics) to predict the appropriate STT-RAM retention times, in order to minimize exploration overhead. We propose an STT-RAM Cache Retention Time (SCART) model, which utilizes machine learning to enable design time or runtime prediction of right-provisioned STT-RAM retention times for latency or energy optimization. Experimental results show that, on average, SCART can reduce the latency and energy by 20.34% and 29.12%, respectively, compared to a homogeneous retention time while reducing the exploration overheads by 52.58% compared to prior work.