HENNC: Hardware Engine for Artificial Neural Network-based Chaotic Oscillators

TL;DR

This paper presents HENNC, a framework that automates the design of FPGA hardware cores for ANN-based chaotic oscillators, improving speed and efficiency over manual methods.

Contribution

It introduces an automated framework for generating FPGA hardware architectures for ANN-based chaotic oscillators, including training, exploration, and code generation.

Findings

Faster hardware design process compared to manual methods

Reduced hardware cost and increased throughput

Open-source implementation available on GitHub

Abstract

This letter introduces a framework for the automatic generation of hardware cores for Artificial Neural Network (ANN)-based chaotic oscillators. The framework trains the model to approximate a chaotic system, then performs design space exploration yielding potential hardware architectures for its implementation. The framework then generates the corresponding synthesizable High-Level Synthesis code and a validation testbench from a selected solution. The hardware design primarily targets FPGAs. The proposed framework offers a rapid hardware design process of candidate architectures superior to manually designed works in terms of hardware cost and throughput. The source code is available on GitHub.