Time performance of Analog Pixel Test Structures with in-chip operational amplifier implemented in 65 nm CMOS imaging process

TL;DR

This paper evaluates the time performance and spatial resolution of analog pixel test structures with in-chip operational amplifiers fabricated in 65 nm CMOS technology, demonstrating high efficiency and sub-100 ps time resolution for high-energy physics applications.

Contribution

It introduces a novel analog pixel test structure with in-chip operational amplifiers in 65 nm CMOS, achieving high time resolution and efficiency in a high-energy physics context.

Findings

Achieved 63 ps time resolution.

Detection efficiency exceeds 99%.

Spatial resolution of 2 μm.

Abstract

In the context of the CERN EP R&D on monolithic sensors and the ALICE ITS3 upgrade, the Tower Partners Semiconductor Co (TPSCo) 65 nm process has been qualified for use in high energy physics, and adopted for the ALICE ITS3 upgrade. An Analog Pixel Test Structure (APTS) featuring fast per pixel operational-amplifier-based buffering for a small matrix of four by four pixels, with a sensor with a small collection electrode and a very non-uniform electric field, was designed to allow detailed characterization of the pixel performance in this technology. Several variants of this chip with different pixel designs have been characterized with a (120 GeV/$c$) positive hadron beam. This result indicates that the APTS-OA prototype variants with the best performance achieve a time resolution of 63 ps with a detection efficiency exceeding 99% and a spatial resolution of 2 $\mu$m, highlighting the potential of TPSCo 65nm CMOS imaging technology for high-energy physics and other fields requiring precise time measurement, high detection efficiency, and excellent spatial resolution.