Improved QLDPC Surgery: Logical Measurements and Bridging Codes

TL;DR

This paper presents an improved QLDPC surgery scheme that reduces resource overhead for fault-tolerant logical measurements, introduces a bridge system for connecting QLDPC codes, and demonstrates practical fault-tolerant gate implementation with simulations.

Contribution

It introduces a gauge-fixed QLDPC surgery scheme with reduced ancilla requirements, a bridge system for universal code connectivity, and a modular decoding algorithm with practical noise simulation.

Findings

Reduced ancilla qubits to $ ext{O}(w)$ for logical measurements.

Achieved fault-tolerant logical Clifford gates on a [[144,12,12]] code.

Demonstrated scheme's practicality through circuit-level noise simulations.

Abstract

In this paper, we introduce the gauge-fixed QLDPC surgery scheme, an improved logical measurement scheme based on the construction of Cohen et al. (Sci. Adv. 8, eabn1717). Our scheme leverages expansion properties of the Tanner graph to substantially reduce the space overhead of QLDPC surgery. In certain cases, we only require $\Theta(w)$ ancilla qubits to fault-tolerantly measure a weight $w$ logical operator. We provide rigorous analysis for the code distance and fault distance of our schemes, and present a modular decoding algorithm that achieves maximal fault-distance. We further introduce a bridge system to facilitate fault-tolerant joint measurements of logical operators. Augmented by this bridge construction, our scheme can be used to connect different families of QLDPC codes into one universal architecture. Applying our toolbox, we show how to perform all logical Clifford gates on the [[144,12,12]] bivariate bicycle code. Our scheme adds 103 ancilla qubits into the connectivity graph, and one of the twelve logical qubits is used as an ancilla for gate synthesis. Logical measurements are combined with the automorphism gates studied by Bravyi et al. (Nature 627, 778-782) to implement 288 Pauli product measurements. We demonstrate the practicality of our scheme through circuit-level noise simulations, leveraging our proposed modular decoder that combines BPOSD with matching.