Latency optimized Deep Neural Networks (DNNs): An Artificial Intelligence approach at the Edge using Multiprocessor System on Chip (MPSoC)

TL;DR

This paper explores low-latency, power-efficient deep neural network implementations on FPGA-based MPSoC systems at the edge, aiming to enhance mobile edge computing performance for latency-critical applications.

Contribution

It demonstrates a hybrid FPGA-based system using Xilinx MPSoC to optimize neural network performance at the edge, combining hardware acceleration with system-level efficiency.

Findings

FPGA-based MPSoC can significantly reduce latency in neural network processing.

Hybrid system design improves power efficiency for mobile edge applications.

Implementation feasibility of neural networks on embedded FPGA devices is validated.

Abstract

Almost in every heavily computation-dependent application, from 6G communication systems to autonomous driving platforms, a large portion of computing should be near to the client side. Edge computing (AI at Edge) in mobile devices is one of the optimized approaches for addressing this requirement. Therefore, in this work, the possibilities and challenges of implementing a low-latency and power-optimized smart mobile system are examined. Utilizing Field Programmable Gate Array (FPGA) based solutions at the edge will lead to bandwidth-optimized designs and as a consequence can boost the computational effectiveness at a system-level deadline. Moreover, various performance aspects and implementation feasibilities of Neural Networks (NNs) on both embedded FPGA edge devices (using Xilinx Multiprocessor System on Chip (MPSoC)) and Cloud are discussed throughout this research. The main goal of this work is to demonstrate a hybrid system that uses the deep learning programmable engine developed by Xilinx Inc. as the main component of the hardware accelerator. Then based on this design, an efficient system for mobile edge computing is represented by utilizing an embedded solution.