Formalizing UML State Machines for Automated Verification -- A Survey

TL;DR

This survey reviews efforts from 1997 to 2021 to formalize UML state machines, aiming to reduce ambiguity and enable automatic verification for early detection of design issues.

Contribution

It provides a comprehensive overview of methods for formalizing UML state machines to facilitate model checking and early vulnerability detection.

Findings

Various formalization approaches have been proposed over the years.

Formalization improves consistency and supports automated verification.

Significant progress has been made in formal semantics for UML state machines.

Abstract

The Unified Modeling Language (UML) is a standard for modeling dynamic systems. UML behavioral state machines are used for modeling the dynamic behavior of object-oriented designs. The UML specification, maintained by the Object Management Group (OMG), is documented in natural language (in contrast to formal language). The inherent ambiguity of natural languages may introduce inconsistencies in the resulting state machine model. Formalizing UML state machine specification aims at solving the ambiguity problem and at providing a uniform view to software designers and developers. Such a formalization also aims at providing a foundation for automatic verification of UML state machine models, which can help to find software design vulnerabilities at an early stage and reduce the development cost. We provide here a comprehensive survey of existing work from 1997 to 2021 related to formalizing UML state machine semantics for the purpose of conducting model checking at the design stage.