A Programming Model for Disaggregated Memory over CXL

TL;DR

This paper introduces CXL0, a novel programming model for disaggregated memory over CXL, enabling reasoning about correctness, durability, and crash consistency in systems utilizing this emerging interconnect standard.

Contribution

CXL0 is the first programming model for concurrent programs over CXL, providing high-level abstractions, formal semantics, and transformations for durability and crash consistency.

Findings

CXL0 captures a wide range of CXL configurations.

Initial measurements on real hardware validate the model.

Transformation improves linearizable algorithms with durability.

Abstract

CXL (Compute Express Link) is an emerging open industry-standard interconnect between processing and memory devices that is expected to revolutionize the way systems are designed. It enables cache-coherent, shared memory pools in a disaggregated fashion at unprecedented scales, allowing algorithms to interact with various storage devices using simple loads and stores. While CXL unleashes unique opportunities, it also introduces challenges of data management and crash consistency. For example, CXL currently lacks an adequate programming model, making it impossible to reason about the correctness and behavior of systems on top. In this work, we present CXL0, the first programming model for concurrent programs over CXL. We propose a high-level abstraction for memory accesses and formally define operational semantics. We demonstrate that CXL0 captures a wide range of current and future CXL setups and perform initial measurements on real hardware. To illustrate the usefulness of CXL0, we present a general transformation that enhances any linearizable concurrent algorithm with durability in a distributed partial-crash setting. We believe that this work will serve as a stepping stone for systems design and programming on top of CXL.