Spin Qubits with Scalable milli-kelvin CMOS Control

TL;DR

This paper demonstrates that milli-kelvin CMOS control circuits can be integrated with silicon spin qubits without degrading their performance, paving the way for scalable quantum computing architectures.

Contribution

It introduces a cryo-CMOS control system at milli-kelvin temperatures that enables scalable, high-density control of spin qubits with minimal impact on qubit fidelity.

Findings

Cryo-CMOS circuits operate effectively at milli-kelvin temperatures.

Single- and two-qubit gate performances are unaffected by the control circuitry.

The platform supports complex, large-scale quantum control architectures.

Abstract

A key virtue of spin qubits is their sub-micron footprint, enabling a single silicon chip to host the millions of qubits required to execute useful quantum algorithms with error correction. With each physical qubit needing multiple control lines however, a fundamental barrier to scale is the extreme density of connections that bridge quantum devices to their external control and readout hardware. A promising solution is to co-locate the control system proximal to the qubit platform at milli-kelvin temperatures, wired-up via miniaturized interconnects. Even so, heat and crosstalk from closely integrated control have potential to degrade qubit performance, particularly for two-qubit entangling gates based on exchange coupling that are sensitive to electrical noise. Here, we benchmark silicon MOS-style electron spin qubits controlled via heterogeneously-integrated cryo-CMOS circuits with a low enough power density to enable scale-up. Demonstrating that cryo-CMOS can efficiently enable universal logic operations for spin qubits, we go on to show that mill-kelvin control has little impact on the performance of single- and two-qubit gates. Given the complexity of our milli-kelvin CMOS platform, with some 100-thousand transistors, these results open the prospect of scalable control based on the tight packaging of spin qubits with a chiplet style control architecture.