Integrated Hardware Architecture and Device Placement Search

TL;DR

This paper presents a novel co-optimization framework for hardware architecture and device placement in distributed deep learning training, leading to improved throughput and resource utilization.

Contribution

It introduces a comprehensive algorithm that jointly optimizes hardware design and device placement, a first in this domain, to enhance training efficiency.

Findings

Achieves higher throughput than TPUv4 and Spotlight.

Effectively balances memory, computation, and data distribution.

Provides open-source implementation of the proposed framework.

Abstract

Distributed execution of deep learning training involves a dynamic interplay between hardware accelerator architecture and device placement strategy. This is the first work to explore the co-optimization of determining the optimal architecture and device placement strategy through novel algorithms, improving the balance of computational resources, memory usage, and data distribution. Our architecture search leverages tensor and vector units, determining their quantity and dimensionality, and on-chip and off-chip memory configurations. It also determines the microbatch size and decides whether to recompute or stash activations, balancing the memory footprint of training and storage size. For each explored architecture configuration, we use an Integer Linear Program (ILP) to find the optimal schedule for executing operators on the accelerator. The ILP results then integrate with a dynamic programming solution to identify the most effective device placement strategy, combining data, pipeline, and tensor model parallelism across multiple accelerators. Our approach achieves higher throughput on large language models compared to the state-of-the-art TPUv4 and the Spotlight accelerator search framework. The entire source code of PHAZE is available at https://github.com/msr-fiddle/phaze.