An Evaluation of Continual Learning for Advanced Node Semiconductor Defect Inspection

TL;DR

This paper proposes a meta-learning approach for continual semiconductor defect inspection that incrementally learns new defect classes, overcoming catastrophic forgetting and data storage issues, and demonstrates superior performance on real SEM datasets.

Contribution

It introduces a task-agnostic meta-learning method enabling scalable, incremental learning of defect classes without extensive data storage, improving robustness in semiconductor defect inspection.

Findings

Outperforms conventional supervised methods on SEM datasets.

Effectively adds new defect classes without catastrophic forgetting.

Scales to multiple process steps with improved accuracy.

Abstract

Deep learning-based semiconductor defect inspection has gained traction in recent years, offering a powerful and versatile approach that provides high accuracy, adaptability, and efficiency in detecting and classifying nano-scale defects. However, semiconductor manufacturing processes are continually evolving, leading to the emergence of new types of defects over time. This presents a significant challenge for conventional supervised defect detectors, as they may suffer from catastrophic forgetting when trained on new defect datasets, potentially compromising performance on previously learned tasks. An alternative approach involves the constant storage of previously trained datasets alongside pre-trained model versions, which can be utilized for (re-)training from scratch or fine-tuning whenever encountering a new defect dataset. However, adhering to such a storage template is impractical in terms of size, particularly when considering High-Volume Manufacturing (HVM). Additionally, semiconductor defect datasets, especially those encompassing stochastic defects, are often limited and expensive to obtain, thus lacking sufficient representation of the entire universal set of defectivity. This work introduces a task-agnostic, meta-learning approach aimed at addressing this challenge, which enables the incremental addition of new defect classes and scales to create a more robust and generalized model for semiconductor defect inspection. We have benchmarked our approach using real resist-wafer SEM (Scanning Electron Microscopy) datasets for two process steps, ADI and AEI, demonstrating its superior performance compared to conventional supervised training methods.