Profiling quantum circuits for their efficient execution on single- and multi-core architectures

TL;DR

This paper introduces graph theory-based metrics to analyze quantum circuits, aiming to predict their performance on various quantum hardware configurations, especially modular multi-core architectures, to improve mapping efficiency and scalability.

Contribution

It presents a novel methodology combining graph metrics with conventional parameters for comprehensive quantum circuit analysis and clustering, enhancing understanding of circuit performance on different quantum devices.

Findings

Graph metrics correlate with quantum circuit mapping performance.

Clustering identifies circuit groups with similar hardware performance.

Analysis supports optimized mapping techniques for modular quantum architectures.

Abstract

Application-specific quantum computers offer the most efficient means to tackle problems intractable by classical computers. Realizing these architectures necessitates a deep understanding of quantum circuit properties and their relationship to execution outcomes on quantum devices. Our study aims to perform for the first time a rigorous examination of quantum circuits by introducing graph theory-based metrics extracted from their qubit interaction graph and gate dependency graph alongside conventional parameters describing the circuit itself. This methodology facilitates a comprehensive analysis and clustering of quantum circuits. Furthermore, it uncovers a connection between parameters rooted in both qubit interaction and gate dependency graphs, and the performance metrics for quantum circuit mapping, across a range of established quantum device and mapping configurations. Among the various device configurations, we particularly emphasize modular (i.e., multi-core) quantum computing architectures due to their high potential as a viable solution for quantum device scalability. This thorough analysis will help us to: i) identify key attributes of quantum circuits that affect the quantum circuit mapping performance metrics; ii) predict the performance on a specific chip for similar circuit structures; iii) determine preferable combinations of mapping techniques and hardware setups for specific circuits; and iv) define representative benchmark sets by clustering similarly structured circuits.