RTL Verification for Secure Speculation Using Contract Shadow Logic

TL;DR

This paper introduces Contract Shadow Logic, a formal verification method that enhances RTL security verification for speculative execution, effectively identifying vulnerabilities and proving security in out-of-order processors.

Contribution

It presents a novel formal verification technique that improves scalability and applicability for checking security properties in hardware designs against speculative attacks.

Findings

Effectively finds attacks on insecure designs

Derives complete proofs for secure designs

Outperforms baseline and state-of-the-art methods

Abstract

Modern out-of-order processors face speculative execution attacks. Despite various proposed software and hardware mitigations to prevent such attacks, new attacks keep arising from unknown vulnerabilities. Thus, a formal and rigorous evaluation of the ability of hardware designs to deal with speculative execution attacks is urgently desired. This paper proposes a formal verification technique called Contract Shadow Logic that can considerably improve RTL verification scalability while being applicable to different defense mechanisms. In this technique, we leverage computer architecture design insights to improve verification performance for checking security properties formulated as software-hardware contracts for secure speculation. Our verification scheme is accessible to computer architects and requires minimal formal-method expertise. We evaluate our technique on multiple RTL designs, including three out-of-order processors. The experimental results demonstrate that our technique exhibits a significant advantage in finding attacks on insecure designs and deriving complete proofs on secure designs, when compared to the baseline and two state-of-the-art verification schemes, LEAVE and UPEC.