Idle is the New Sleep: Configuration-Aware Alternative to Powering Off FPGA-Based DL Accelerators During Inactivity

TL;DR

This paper presents a configuration-aware idle strategy for FPGA-based deep learning accelerators that significantly reduces energy consumption and extends system lifetime in IoT applications.

Contribution

It introduces an optimized idle-waiting approach that minimizes configuration energy overhead and outperforms traditional power-off methods in energy efficiency.

Findings

Achieved a 40.13-fold reduction in configuration energy.

Extended system lifetime by approximately 12.39x compared to on-off strategy.

Validated improvements through hardware measurements and simulations.

Abstract

In the rapidly evolving Internet of Things (IoT) domain, we concentrate on enhancing energy efficiency in Deep Learning accelerators on FPGA-based heterogeneous platforms, aligning with the principles of sustainable computing. Instead of focusing on the inference phase, we introduce innovative optimizations to minimize the overhead of the FPGA configuration phase. By fine-tuning configuration parameters correctly, we achieved a 40.13-fold reduction in configuration energy. Moreover, augmented with power-saving methods, our Idle-Waiting strategy outperformed the traditional On-Off strategy in duty-cycle mode for request periods up to 499.06 ms. Specifically, at a 40 ms request period within a 4147 J energy budget, this strategy extends the system lifetime to approximately 12.39x that of the On-Off strategy. Empirically validated through hardware measurements and simulations, these optimizations provide valuable insights and practical methods for achieving energy-efficient and sustainable deployments in IoT.