Assessing the Performance of Stateful Logic in 1-Selector-1-RRAM Crossbar Arrays

TL;DR

This paper analyzes the performance of active 1-selector-1-RRAM crossbar arrays with VO2-based selectors, focusing on their in-memory computation capabilities and comparing them to passive arrays.

Contribution

It introduces a comprehensive model for 1S1R arrays with VO2 selectors and provides detailed simulations across various array sizes, evaluating logic performance and advantages over passive arrays.

Findings

Active 1S1R arrays mitigate sneak path issues effectively.

Simulations show improved readout margins and reduced power consumption.

Performance varies with array size and device parameters.

Abstract

Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO2-based selector and TiN/TiOx/HfOx/Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from $4\times4$ to $512\times512$. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.