Towards Efficient Design Verification -- Constrained Random Verification using PyUVM

TL;DR

This paper evaluates the effectiveness of Python-based verification environments, specifically PyUVM, in design verification, comparing their performance and features to traditional SystemVerilog-UVM methods.

Contribution

It provides a comprehensive comparison of PyUVM and SystemVerilog-UVM, highlighting Python's potential in reducing setup costs and accelerating test development.

Findings

PyUVM offers comparable verification capabilities to SystemVerilog-UVM.

Python-based tools can reduce verification setup time.

PyUVM demonstrates promising performance across various IPs.

Abstract

Python, as a multi-paradigm language known for its ease of integration with other languages, has gained significant attention among verification engineers recently. A Python-based verification environment capitalizes on open-source frameworks such as PyUVM providing Python-based UVM 1.2 implementation and PyVSC facilitating constrained randomization and functional coverage. These libraries play a pivotal role in expediting test development and hold promise for reducing setup costs. The goal of this paper is to evaluate the effectiveness of PyUVM verification testbenches across various design IPs, aiming for a comprehensive comparison of their features and performance metrics with the established SystemVerilog-UVM methodology.