Effective Design Verification -- Constrained Random with Python and Cocotb

TL;DR

This paper evaluates the effectiveness of a Python-based verification environment using Cocotb for hardware design verification, comparing it with traditional SystemVerilog methods in terms of features and performance.

Contribution

It provides an assessment of Python-Cocotb verification setup's effectiveness and compares its performance and features with SystemVerilog-based verification.

Findings

Python-Cocotb simplifies testbench development.

It reduces setup costs compared to traditional methods.

Performance metrics are comparable or superior to SystemVerilog.

Abstract

Being the most widely used language across the world due to its simplicity and with 35 keywords (v3.7), Python attracts both hardware and software engineers. Python-based verification environment leverages open-source libraries such as cocotb and cocotb-coverage that enables interfacing the tesbenches with any available simulator and facilitating constrained randomization, coverage respectively. These libraries significantly ease the development of testbenches and have the potential to reduce the setup cost. The goal of this paper is to assess the effectiveness of a Python-Cocotb verification setup with design IPs and compare its features and performance metrics with the current de-facto hardware verification language i.e., SystemVerilog.