Switch-Less Dragonfly on Wafers: A Scalable Interconnection Architecture based on Wafer-Scale Integration

TL;DR

This paper introduces a wafer-scale interconnection architecture called Switch-Less-Dragonfly-on-Wafers that eliminates high-radix switches, reducing costs and latency while improving throughput in high-performance computing systems.

Contribution

It proposes a scalable wafer-based interconnection architecture that replaces high-radix switches with distributed networks-on-chip, along with deadlock-free routing algorithms, enhancing performance and reducing costs.

Findings

Outperforms traditional switch-based Dragonfly in cost and performance.

Eliminates high-radix switches, reducing latency and energy overhead.

Supports scalable, high-bandwidth connectivity for large-scale supercomputers.

Abstract

Existing high-performance computing (HPC) interconnection architectures are based on high-radix switches, which limits the injection/local performance and introduces latency/energy/cost overhead. The new wafer-scale packaging and high-speed wireline technologies provide high-density, low-latency, and high-bandwidth connectivity, thus promising to support direct-connected high-radix interconnection architecture. In this paper, we propose a wafer-based interconnection architecture called Switch-Less-Dragonfly-on-Wafers. By utilizing distributed high-bandwidth networks-on-chip-on-wafer, costly high-radix switches of the Dragonfly topology are eliminated while increasing the injection/local throughput and maintaining the global throughput. Based on the proposed architecture, we also introduce baseline and improved deadlock-free minimal/non-minimal routing algorithms with only one additional virtual channel. Extensive evaluations show that the Switch-Less-Dragonfly-on-Wafers outperforms the traditional switch-based Dragonfly in both cost and performance. Similar approaches can be applied to other switch-based direct topologies, thus promising to power future large-scale supercomputers.