Parallel Ising Annealer via Gradient-based Hamiltonian Monte Carlo

TL;DR

This paper introduces a scalable, FPGA-based Ising annealer using gradient-based Hamiltonian Monte Carlo, demonstrating superior performance and scalability on benchmark problems compared to existing quantum and classical hardware.

Contribution

It presents a novel parallel Ising annealer leveraging gradient-based Hamiltonian Monte Carlo, enabling scalable, hardware-efficient optimization on FPGAs with competitive performance.

Findings

Achieved up to 200 spins on FPGA with better performance than D-Wave 2000Q.

Demonstrated scalability and efficiency on various benchmark problems.

Showed potential for classical hardware to rival quantum annealers.

Abstract

Ising annealer is a promising quantum-inspired computing architecture for combinatorial optimization problems. In this paper, we introduce an Ising annealer based on the Hamiltonian Monte Carlo, which updates the variables of all dimensions in parallel. The main innovation is the fusion of an approximate gradient-based approach into the Ising annealer which introduces significant acceleration and allows a portable and scalable implementation on the commercial FPGA. Comprehensive simulation and hardware experiments show that the proposed Ising annealer has promising performance and scalability on all types of benchmark problems when compared to other Ising annealers including the state-of-the-art hardware. In particular, we have built a prototype annealer which solves Ising problems of both integer and fraction coefficients with up to 200 spins on a single low-cost FPGA board, whose performance is demonstrated to be better than the state-of-the-art quantum hardware D-Wave 2000Q and similar to the expensive coherent Ising machine. The sub-linear scalability of the annealer signifies its potential in solving challenging combinatorial optimization problems and evaluating the advantage of quantum hardware.