Design of an 8-Channel 40 GS/s 20 mW/Ch Waveform Sampling ASIC in 65 nm CMOS

TL;DR

This paper presents the preliminary design of an 8-channel, 40 GS/s waveform sampling ASIC in 65 nm CMOS technology, achieving 1 ps timing resolution with low power consumption for particle detection applications.

Contribution

It introduces a novel 8-channel waveform sampling ASIC with fast and slow SCAs, enabling high-resolution timing and long buffer length in 65 nm CMOS.

Findings

Achieves 1 ps timing resolution at 20 mW per channel.

Supports 40 GS/s sampling rate with 4 GHz bandwidth.

Features a dead time of 20 microseconds and 50 kHz readout rate.

Abstract

1 ps timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe a preliminary design for PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in the TSMC 65 nm process targetting 1 ps resolution at 20 mW power per channel. Each channel consists of four fast and one slow switched capacitor arrays (SCA), allowing ps time resolution combined with a long effective buffer. Each fast SCA is 1.6 ns long and has a nominal sampling rate of 40 GS/s. The slow SCA is 204.8 ns long and samples at 5 GS/s. Recording of the analog data for each channel is triggered by a fast discriminator capable of multiple triggering during the window of the slow SCA. To achieve a large dynamic range, low leakage, and high bandwidth, the SCA sampling switches are implemented as 2.5 V nMOSFETs controlled by 1.2 V shift registers. Stored analog data are digitized by an external ADC at 10 bits or better. Specifications on operational parameters include a 4 GHz analog bandwidth and a dead time of 20 microseconds, corresponding to a 50 kHz readout rate, determined by the choice of the external ADC.