Resource-aware scheduling of multiple quantum circuits on a hardware device

TL;DR

This paper addresses resource-aware scheduling of multiple quantum circuits on hardware, optimizing for maximum parallel execution while maintaining layout quality and minimizing noise, using ILP and heuristic methods.

Contribution

It introduces an ILP formulation for scheduling quantum circuits with layout constraints and proposes a greedy heuristic for improved hardware utilization.

Findings

ILP formulation ensures maximum fidelity and layout constraints.

Heuristic method doubles or triples hardware utilization for large devices.

Comprehensive experiments validate the approach on quantum circuit benchmarks.

Abstract

Recent quantum technologies and quantum error-correcting codes emphasize the requirement for arranging interacting qubits in a nearest-neighbor (NN) configuration while mapping a quantum circuit onto a given hardware device, in order to avoid undesirable noise. It is equally important to minimize the wastage of qubits in a quantum hardware device with m qubits while running circuits of n qubits in total, with n < m. In order to prevent cross-talk between two circuits, a buffer distance between their layouts is needed. Furthermore, not all the qubits and all the two-qubit interactions are at the same noise-level. Scheduling multiple circuits on the same hardware may create a possibility that some circuits are executed on a noisier layout than the others. In this paper, we consider an optimization problem which schedules as many circuits as possible for execution in parallel on the hardware, while maintaining a pre-defined layout quality for each. An integer linear programming formulation to ensure maximum fidelity while preserving the nearest neighbor arrangement among interacting qubits is presented. Our assertion is supported by comprehensive investigations involving various well-known quantum circuit benchmarks. As this scheduling problem is shown to be NP Hard, we also propose a greedy heuristic method which provides 2x and 3x better utilization for 27-qubit and 127-qubit hardware devices respectively in terms of qubits and time.