Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC
Michael Rogenmoser, Philip Wiese, Bruno Endres Forlin, Frank K. G\"urkaynak, Paolo Rech, Alessandra Menicucci, Marco Ottavi, Luca Benini

TL;DR
This paper presents the design and experimental evaluation of a fault-tolerant 28nm RISC-V SoC, demonstrating its robustness against radiation-induced faults through physical testing and simulation, with novel fault correction mechanisms.
Contribution
It introduces a new fault-tolerant RISC-V SoC design with validated error correction mechanisms and provides comprehensive experimental characterization under radiation exposure.
Findings
Error correction in memory is highly effective with up to 99.10% correct results.
Triple-core lockstep mechanism corrects errors with a cross-section up to 3.23e-11 cm^2.
Remaining uncorrectable vulnerability is below 5.36e-12 cm^2.
Abstract
RISC-V-based fault-tolerant system-on-chip (SoC) designs are critical for the new generation of automotive and space SoC architectures. However, reliability assessment requires characterization under controlled radiation doses to accurately quantify the fault tolerance of the fabricated designs. This work analyzes the Trikarenos design, a SoC implemented in TSMC 28nm, for single event upset (SEU) vulnerability under atmospheric neutron and 200 MeV proton radiation, comparing these results to simulation-based fault injection. All faults in error correction codes (ECC) protected memory are corrected by a scrubber, showing an estimated cross-section per bit of up to cm bit. Furthermore, the triple-core lockstep (TCLS) mechanism implemented in Trikarenos is validated and is shown to correct errors affecting a cross-section up to …
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Taxonomy
TopicsVLSI and Analog Circuit Testing · Integrated Circuits and Semiconductor Failure Analysis · Radiation Effects in Electronics
