Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures

TL;DR

This paper enhances the ESP platform to enable flexible, efficient, and scalable on-chip communication for programmable accelerators in heterogeneous SoCs, supporting various communication modes and synchronization methods.

Contribution

It introduces new communication mechanisms, multicast support, synchronization leveraging coherence, and ISA extensions, with minimal area overhead and validation on FPGA prototypes.

Findings

Supports flexible point-to-point communication

Enables multicast data forwarding to multiple accelerators

Validated features on FPGA prototypes

Abstract

We present several enhancements to the open-source ESP platform to support flexible and efficient on-chip communication for programmable accelerators in heterogeneous SoCs. These enhancements include 1) a flexible point-to-point communication mechanism between accelerators, 2) a multicast NoC that supports data forwarding to multiple accelerators simultaneously, 3) accelerator synchronization leveraging the SoC's coherence protocol, 4) an accelerator interface that offers fine-grained control over the communication mode used, and 5) an example ISA extension to support our enhancements. Our solution adds negligible area to the SoC architecture and requires minimal changes to the accelerators themselves. We have validated most of these features in complex FPGA prototypes and plan to include them in the open-source release of ESP in the coming months.