Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs

TL;DR

This paper proposes a novel FPGA multiplier design that combines smaller Booth-Arrays with tiling methods to optimize the trade-off between area and delay, effectively utilizing DSP and LUT resources.

Contribution

It introduces a hybrid multiplier architecture using smaller Booth-Arrays integrated into tiling-based methods to improve efficiency and resource utilization on FPGAs.

Findings

Reduced critical path delay compared to large Booth-Arrays

Significant LUT resource savings over previous tiling methods

Achieved better area-delay trade-offs with configurable DSP usage

Abstract

The major challenge when designing multipliers for FPGAs is to address several trade-offs: On the one hand at the performance level and on the other hand at the resource level utilizing DSP blocks or look-up tables (LUTs). With DSPs being a relatively limited resource, the problem of under- or over-utilization of DSPs has previously been addressed by the concept of multiplier tiling, by assembling multipliers from DSPs and small supplemental LUT multipliers. But there had always been an efficiency gap between tiling-based multipliers and radix-4 Booth-Arrays. While the monolithic Booth-Array was shown to be considerably more efficient in terms of LUT-resources on many modern FPGA-architectures, it typically possess a significantly higher critically path delay (or latency when pipelined) compared to multipliers designed by tiling. This work proposes and analyzes the use of smaller Booth-Arrays as sub-multipliers that are integrated into existing tiling-based methods, such that better trade-off points between area and delay can be reached while utilizing a user-specified number of DSP blocks. It is shown by synthesis experiments, that the critical path delay compared to large Booth-Arrays can be reduced, while achieving significant reductions in LUT-resources compared to previous tiling.