NeuroSteiner: A Graph Transformer for Wirelength Estimation

TL;DR

NeuroSteiner is a neural network model that accurately estimates wirelength in chip placement by learning from an optimal solver, enabling faster and precise wirelength minimization through differentiable gradient-based placement.

Contribution

It introduces NeuroSteiner, a neural model that distills an optimal RSMT solver, enabling fast, accurate wirelength estimation and gradient-based placement without extensive real chip data.

Findings

Achieves 0.3% WL error on benchmark datasets.

Runs 60% faster than GeoSteiner for wirelength estimation.

Enables gradient-based placement minimizing wirelength effectively.

Abstract

A core objective of physical design is to minimize wirelength (WL) when placing chip components on a canvas. Computing the minimal WL of a placement requires finding rectilinear Steiner minimum trees (RSMTs), an NP-hard problem. We propose NeuroSteiner, a neural model that distills GeoSteiner, an optimal RSMT solver, to navigate the cost--accuracy frontier of WL estimation. NeuroSteiner is trained on synthesized nets labeled by GeoSteiner, alleviating the need to train on real chip designs. Moreover, NeuroSteiner's differentiability allows to place by minimizing WL through gradient descent. On ISPD 2005 and 2019, NeuroSteiner can obtain 0.3% WL error while being 60% faster than GeoSteiner, or 0.2% and 30%.