RISC-V R-Extension: Advancing Efficiency with Rented-Pipeline for Edge DNN Processing

TL;DR

This paper presents the RISC-V R-extension, a novel architectural enhancement with rented-pipeline stages and custom instructions, significantly improving DNN inference efficiency on edge devices by reducing latency and memory access.

Contribution

It introduces the RISC-V R-extension with rented-pipeline and custom instructions, advancing edge DNN processing efficiency beyond traditional architectures.

Findings

Reduced latency in DNN inference

Lower memory access frequency

Enhanced processing responsiveness

Abstract

The proliferation of edge devices necessitates efficient computational architectures for lightweight tasks, particularly deep neural network (DNN) inference. Traditional NPUs, though effective for such operations, face challenges in power, cost, and area when integrated into lightweight edge devices. The RISC-V architecture, known for its modularity and open-source nature, offers a viable alternative. This paper introduces the RISC-V R-extension, a novel approach to enhancing DNN process efficiency on edge devices. The extension features rented-pipeline stages and architectural pipeline registers (APR), which optimize critical operation execution, thereby reducing latency and memory access frequency. Furthermore, this extension includes new custom instructions to support these architectural improvements. Through comprehensive analysis, this study demonstrates the boost of R-extension in edge device processing, setting the stage for more responsive and intelligent edge applications.