FFT and Linear Convolution Implementation with Bit Slicing Multiplier: A Novel Approach

TL;DR

This paper explores integrating Bit Slicing Multiplier (BSM) techniques into FFT and linear convolution algorithms, demonstrating improved speed and resource efficiency for FPGA-based digital signal processing applications.

Contribution

It introduces a novel BSM-based approach for FFT and convolution, enhancing computational efficiency and resource utilization in FPGA implementations.

Findings

BSM improves processing speed in FFT and convolution

Resource utilization is reduced with BSM integration

Experimental results show superior performance over traditional methods

Abstract

This paper presents a comprehensive exploration of Fast Fourier Transform (FFT) and linear convolution implementations, integrating both conventional methods and novel approaches leveraging the Bit Slicing Multiplier (BSM) technique. The Bit Slicing Multiplier utilizes Look-Up Tables (LUTs) to execute bitwise operations in parallel, offering efficient arithmetic operations ideally suited for digital signal processing tasks. We extensively investigate the integration of BSM into FFT and linear convolution algorithms, emphasizing its advantages in terms of speed and resource utilization. Additionally, we introduce our own innovative ideas for FFT and convolution algorithms, contributing to the broader discourse on efficient signal processing techniques. Experimental validation of our implementations is conducted using Vivado, a leading FPGA synthesis and implementation tool. Comparative analysis demonstrates the superior performance of our BSM-enhanced approaches, showcasing their potential for real-time signal processing applications. This study not only advances the understanding of FFT and convolution implementations but also highlights the effectiveness of novel techniques like BSM in enhancing computational efficiency in FPGA-based systems.