Multi-Objective Optimization for Common-Centroid Placement of Analog Transistors

TL;DR

This paper introduces a multi-objective optimization framework for common-centroid placement of analog transistors, effectively handling multiple layout constraints and exploring more topologies for improved circuit performance.

Contribution

It presents a novel unified optimization approach that automates CC transistor placement considering various constraints, surpassing manual and existing methods in solution quality.

Findings

Better circuit performance in post-layout simulations

More comprehensive exploration of CC topologies

Outperforms state-of-the-art techniques in layout quality

Abstract

In analog circuits, process variation can cause unpredictability in circuit performance. Common-centroid (CC) type layouts have been shown to mitigate process-induced variations and are widely used to match circuit elements. Nevertheless, selecting the most suitable CC topology necessitates careful consideration of important layout constraints. Manual handling of these constraints becomes challenging, especially with large size problems. State-of-the-art CC placement methods lack an optimization framework to handle important layout constraints collectively. They also require manual efforts and consequently, the solutions can be suboptimal. To address this, we propose a unified framework based on multi-objective optimization for CC placement of analog transistors. Our method handles various constraints, including degree of dispersion, routing complexity, diffusion sharing, and layout dependent effects. The multi-objective optimization provides better handling of the objectives when compared to single-objective optimization. Moreover, compared to existing methods, our method explores more CC topologies. Post-layout simulation results show better performance compared to state-of-the-art techniques in generating CC layouts.