An Open-Source Fast Parallel Routing Approach for Commercial FPGAs

TL;DR

This paper introduces an open-source parallel routing method for commercial FPGAs that significantly speeds up routing and improves wirelength compared to existing tools, addressing the increasing complexity of FPGA designs.

Contribution

It presents a novel recursive partitioning ternary tree for parallel routing and a hybrid congestion updating strategy, advancing FPGA routing efficiency.

Findings

Achieves 2x speedup over serial router RWRoute

Delivers 2x acceleration compared to Vivado

Reduces critical-path wirelength by 31%

Abstract

In the face of escalating complexity and size of contemporary FPGAs and circuits, routing emerges as a pivotal and time-intensive phase in FPGA compilation flows. In response to this challenge, we present an open-source parallel routing methodology designed to expedite routing procedures for commercial FPGAs. Our approach introduces a novel recursive partitioning ternary tree to augment the parallelism of multi-net routing. Additionally, we propose a hybrid updating strategy for congestion coefficients within the routing cost function to accelerate congestion resolution in negotiation-based routing algorithms. Evaluation on public benchmarks from the FPGA24 routing contest demonstrates the efficacy of our parallel router. It achieves a 2x speedup compared to the academic serial router RWRoute. Furthermore, when compared to the industry-standard tool Vivado, our approach not only delivers a 2x acceleration but also yields a notable 31% enhancement in critical-path wirelength.