Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution
Rahul Bera, Adithya Ranganathan, Joydeep Rakshit, Sujit Mahto, Anant, V. Nori, Jayesh Gaur, Ataberk Olgun, Konstantinos Kanellopoulos, Mohammad, Sadrosadati, Sreenivas Subramoney, Onur Mutlu

TL;DR
Constable is a microarchitectural technique that safely eliminates redundant load instruction executions, improving performance and power efficiency by dynamically identifying and skipping stable loads.
Contribution
It introduces a novel method to eliminate load execution for likely-stable loads, mitigating both data and resource load dependencies.
Findings
Performance improved by 5.1% on average
Core dynamic power reduced by 3.4%
Performance gains increase to 8.8% with SMT
Abstract
Load instructions often limit instruction-level parallelism (ILP) in modern processors due to data and resource dependences they cause. Prior techniques like Load Value Prediction (LVP) and Memory Renaming (MRN) mitigate load data dependence by predicting the data value of a load instruction. However, they fail to mitigate load resource dependence as the predicted load instruction gets executed nonetheless. Our goal in this work is to improve ILP by mitigating both load data dependence and resource dependence. To this end, we propose a purely-microarchitectural technique called Constable, that safely eliminates the execution of load instructions. Constable dynamically identifies load instructions that have repeatedly fetched the same data from the same load address. We call such loads likely-stable. For every likely-stable load, Constable (1) tracks modifications to its source…
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Taxonomy
TopicsElevator Systems and Control
