Resilient and Secure Programmable System-on-Chip Accelerator Offload

TL;DR

Samsara introduces a secure, resilient platform for programmable hardware accelerators like FPGAs, using lightweight BFT protocols and rejuvenation techniques to ensure integrity and low latency despite malicious components.

Contribution

It presents Samsara, the first system combining hardware-based BFT protocols and rejuvenation to enhance resilience and security in programmable SoC accelerators.

Findings

Achieves low-latency Byzantine fault tolerance in FPGA-based systems.

Supports hardware rejuvenation for fault mitigation.

Maintains security and resilience with minimal latency overhead.

Abstract

Computational offload to hardware accelerators is gaining traction due to increasing computational demands and efficiency challenges. Programmable hardware, like FPGAs, offers a promising platform in rapidly evolving application areas, with the benefits of hardware acceleration and software programmability. Unfortunately, such systems composed of multiple hardware components must consider integrity in the case of malicious components. In this work, we propose Samsara, the first secure and resilient platform that derives, from Byzantine Fault Tolerant (BFT), protocols to enhance the computing resilience of programmable hardware. Samsara uses a novel lightweight hardware-based BFT protocol for Systems-on-Chip, called H-Quorum, that implements the theoretical-minimum latency between applications and replicated compute nodes. To withstand malicious behaviors, Samsara supports hardware rejuvenation, which is used to replace, relocate, or diversify faulty compute nodes. Samsara's architecture ensures the security of the entire workflow while keeping the latency overhead, of both computation and rejuvenation, close to the non-replicated counterpart.