Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor

TL;DR

This paper presents the design, implementation, and evaluation of an extension to the RISC-V processor's MMU to efficiently manage 64KB pages alongside 4KB pages, aiming to reduce performance overhead under heavy memory loads.

Contribution

It introduces a novel extension to the RISC-V MMU for managing larger pages in the L2 TLB, addressing design challenges and trade-offs involved.

Findings

Preliminary sensitivity analysis of L2 TLB configurations

Trade-offs in page size management for performance optimization

Potential techniques for further improving memory management

Abstract

The RISC-V SVNAPOT Extension aims to remedy the performance overhead of the Memory Management Unit (MMU), under heavy memory loads. The Privileged Specification defines additional Natural-Power-of-Two (NAPOT) multiples of the 4KB base page size, with 64KB as the default candidate. In this paper we extend the MMU of the Rocket Chip Generator, in order to manage the collocation of 64KB pages along with 4KB pages in the L2 TLB. We present the design challenges we had to overcome and the trade-offs of our design choices. We conduct a preliminary sensitivity analysis of the L2 TLB with different configurations/page sizes. Finally, we summarize on techniques which could further improve memory management performance on RISC-V systems.