Hypervisor Extension for a RISC-V Processor

TL;DR

This paper discusses the design and implementation of a hypervisor extension for a 64-bit RISC-V processor, detailing the process and key components involved.

Contribution

It presents the first detailed account of developing a hypervisor extension specifically for RISC-V architecture.

Findings

Successful implementation of hypervisor extension on RISC-V

Key components and design considerations outlined

Provides a foundation for virtualization on RISC-V processors

Abstract

This paper describes our experience implementing a Hypervisor extension for a 64-bit RISC-V processor. We describe the design process and the main required parts with a brief explanation of each one.