Enhancing and Mapping Thermal Boundary Conductance across Bonded Si/SiC Interface

TL;DR

This study demonstrates a significant enhancement in thermal boundary conductance at the Si/SiC interface using room-temperature bonding and annealing, with detailed spatial mapping revealing distribution variations crucial for thermal management design.

Contribution

It introduces a novel bonding and annealing process to improve and map the TBC across Si/SiC interfaces at wafer scale, providing insights into spatial distribution effects.

Findings

TBC increased from 109 to 293 MW/m2K after annealing.

Absence of oxide layer enhances TBC.

Spatial distribution of TBC varies with annealing.

Abstract

SiC is a promising substrate for Si-on-insulator (SOI) wafers for efficient thermal management owing to its high thermal conductivity and large bandgap. However, fabricating a Si device layer on a SiC substrate with a high and uniform thermal-boundary conductance (TBC) at the wafer scale is challenging. In this study, a 4-inch Si-on-SiC wafer was fabricated using a room-temperature surface-activated bonding method, and the TBC was measured using the time-domain thermoreflectance (TDTR) method. The obtained TBC was 109 MW/m2K in the as-bonded sample, improving to 293 MW/m2K after annealing at 750 oC, representing a 78% increase compared to previously reported values for a Si-SiC interface formed by bonding methods. Such enhancement is attributed to the absence of an oxide layer at the interface. Furthermore, we assessed the actual spatial distribution of the TBC in the SOI system by combining the TDTR mapping with a mathematical model to remove the influence of random errors in the experiment. The spatial distributions before and after annealing were 7% and 17%, respectively. Such variation highlights the need to consider the TBC distribution when designing thermal management systems.