Impact of the Top SiO2 Interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure

TL;DR

This study explores how varying the top SiO2 interlayer thickness affects the memory window of Si channel FeFETs with a specific gate structure, revealing a two-stage linear increase and trade-offs with endurance, aiding device design.

Contribution

It demonstrates the relationship between SiO2 interlayer thickness and memory window, and shows how inserting a dielectric layer improves device performance and longevity.

Findings

Memory window increases with SiO2 thickness in two linear stages.

Endurance degrades as initial memory window increases.

Inserting a 3.4 nm SiO2 layer achieves a 6.3 V memory window with over 10-year retention.

Abstract

We study the impact of top SiO2 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistor (FeFET) with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. We find that the MW increases with the increasing thickness of the top SiO2 interlayer, and such an increase exhibits a two-stage linear dependence. The physical origin is the presence of the different interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface. Moreover, we investigate the dependence of endurance characteristics on initial MW. We find that the endurance characteristic degrades with increasing the initial MW. By inserting a 3.4 nm SiO2 dielectric interlayer between the gate metal TiN and the ferroelectric Hf0.5Zr0.5O2, we achieve a MW of 6.3 V and retention over 10 years. Our work is helpful in the device design of FeFET.