A Cryogenic readout integrated circuit with analog pile-up and in-Pixel ADC for high frame rate Skipper CCD-in-CMOS Sensors
Adam Quinn (1), Farah Fahim (1), Davide Braga (1) ((1) Fermi National, Accelerator Laboratory)

TL;DR
This paper presents a cryogenic, high-speed readout circuit with in-pixel ADC and analog pile-up for Skipper CCD-in-CMOS sensors, enabling high frame rates and low noise in large-area imaging.
Contribution
It introduces a novel in-pixel SAR ADC with analog pile-up for high frame rate Skipper CCD-in-CMOS sensors, optimizing power and noise performance.
Findings
Achieved 4 kfps frame rate with large sensor arrays
Demonstrated ADC DNL of ~0.44 LSB and INL of 0.58 LSB
Power consumption estimated at 50μW per pixel
Abstract
The Skipper CCD-in-CMOS Parallel Read-Out Circuit V2 (SPROCKET2) is designed to enable high frame rate readout of Skipper CCD-in-CMOS image sensors. The SPROCKET2 pixel is fabricated in a 65 nm CMOS process and occupies a 60m 60m footprint. SPROCKET2 is intended to be heterogeneously integrated with a pixelated Skipper CCD-in-CMOS sensor, such that one readout pixel is connected to a multiplexed array of 16 active image sensor pixels, to match their spatial geometry. Our design benefits from the Skipper CCD-in-CMOS sensor's non-destructive readout capability to achieve exceptionally low noise through multi-sampling and averaging while optimizing for total power consumption. The pixel readout utilizes correlated double sampling to minimize 1/f noise and includes "pile-up" of ten successive samples in the analog domain before digitizing at a rate of 66.7 ksps.…
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Taxonomy
TopicsCCD and CMOS Imaging Sensors · Infrared Target Detection Methodologies · Photocathodes and Microchannel Plates
