Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS

TL;DR

Basilisk is the first fully open-source, Linux-capable RISC-V SoC taped out in 130nm CMOS, demonstrating the feasibility of end-to-end open-source hardware at a complex, high-performance level.

Contribution

It introduces Basilisk, the first end-to-end open-source RISC-V SoC with Linux support, and develops a reusable tool pipeline for converting industry-grade RTL to open-source formats.

Findings

Achieved 77 MHz clock speed with open-source synthesis optimization

Reduced cell area by 1.6x and die area by 12% through optimization

Enabled zero DRC violations in place and route process

Abstract

Open-source hardware (OSHW) is rapidly gaining traction in academia and industry. The availability of open RTL descriptions, EDA tools, and even PDKs enables a fully auditable supply chain for end-to-end (RTL to layout) open-source silicon, significantly strengthening security and transparency. Despite promising developments, existing OSHW efforts have so far fallen short of producing end-to-end open-source SoCs at the complexity and performance level needed to run a general-purpose OS. We present Basilisk, the first end-to-end open-source, Linux-capable RISC-V SoC taped out in IHP's open 130 nm technology. Basilisk features a 64-bit RISC-V core, a fully digital HyperRAM DRAM controller, and a rich set of IO peripherals including USB 1.1 and VGA. To tape out Basilisk, we create a reusable tool pipeline to convert its industry-grade SystemVerilog description to Verilog. We optimized logic synthesis in the open source Yosys synthesis tool, obtaining an increase in Basilisk's peak clock speed by 2.3x to 77 MHz and reducing its cell area by 1.6x to 1.1 MGE while also reducing synthesis runtime and RAM usage. We further optimized place and route in OpenROAD, enabling convergence to zero DRC violations while increasing core area utilization by 10% and reducing die area by 12%.