RISC-V processor enhanced with a dynamic micro-decoder unit

TL;DR

This paper explores integrating a dynamic micro-decoder unit into RISC-V processors to enhance instruction execution flexibility, security, and energy efficiency, by enabling custom instruction sequences at a specific pipeline stage.

Contribution

It introduces a novel micro-decoder unit inspired by CISC processors into RISC-V cores, enabling dynamic execution of custom instruction sequences.

Findings

Improved support for custom instruction sequences.

Potential benefits in security and energy efficiency.

Analysis of integration costs and benefits.

Abstract

For years, the open-source RISC-V instruction set has been driving innovation in processor design, spanning from high-end cores to low-cost or low-power cores. After a decade of evolution, RISC architectures are now as mature as the CISC architectures popularized by industry giant Intel. Security and energy efficiency are now joining execution speed among the design constraints. In this article, we assess the benefits and costs associated with integrating a micro-decoding unit inspired by CISC processors into a RISC-V core. This unit, added in a specific pipeline stage, should enable dynamic custom instruction sequences execution whose usage could be, for instance to compress binaries, obfuscate behavior, etc.