Enhancing Dropout-based Bayesian Neural Networks with Multi-Exit on FPGA

TL;DR

This paper introduces a novel FPGA-based acceleration framework for dropout-based Bayesian neural networks with multi-exit architecture, significantly improving energy efficiency and performance for safety-critical applications.

Contribution

It presents a combined algorithm and hardware co-design approach, including a multi-exit dropout Bayesian neural network and an FPGA accelerator generation framework.

Findings

Achieves higher energy efficiency than CPU, GPU, and existing hardware implementations.

Reduces computational and memory overheads while maintaining high accuracy.

Provides an open-source FPGA acceleration framework for efficient Bayesian neural networks.

Abstract

Reliable uncertainty estimation plays a crucial role in various safety-critical applications such as medical diagnosis and autonomous driving. In recent years, Bayesian neural networks (BayesNNs) have gained substantial research and industrial interests due to their capability to make accurate predictions with reliable uncertainty estimation. However, the algorithmic complexity and the resulting hardware performance of BayesNNs hinder their adoption in real-life applications. To bridge this gap, this paper proposes an algorithm and hardware co-design framework that can generate field-programmable gate array (FPGA)-based accelerators for efficient BayesNNs. At the algorithm level, we propose novel multi-exit dropout-based BayesNNs with reduced computational and memory overheads while achieving high accuracy and quality of uncertainty estimation. At the hardware level, this paper introduces a transformation framework that can generate FPGA-based accelerators for the proposed efficient multi-exit BayesNNs. Several optimization techniques such as the mix of spatial and temporal mappings are introduced to reduce resource consumption and improve the overall hardware performance. Comprehensive experiments demonstrate that our approach can achieve higher energy efficiency compared to CPU, GPU, and other state-of-the-art hardware implementations. To support the future development of this research, we have open-sourced our code at: https://github.com/os-hxfan/MCME_FPGA_Acc.git