Hardware-Efficient Randomized Compiling

TL;DR

This paper presents a hardware-efficient algorithm for randomized compiling that reduces runtime and variance in quantum circuit measurements by implementing cycle-by-cycle randomizations directly on FPGA hardware.

Contribution

It introduces a novel FPGA-based algorithm for randomized compiling that operates with zero runtime overhead and per-shot randomization, improving efficiency in quantum error mitigation.

Findings

Significant reduction in circuit runtime with RC

Lower variance in measured observables

Successful implementation on QubiC hardware

Abstract

Randomized compiling (RC) is an efficient method for tailoring arbitrary Markovian errors into stochastic Pauli channels. However, the standard procedure for implementing the protocol in software comes with a large experimental overhead -- namely, it scales linearly in the number of desired randomizations, each of which must be generated and measured independently. In this work, we introduce a hardware-efficient algorithm for performing RC on a cycle-by-cycle basis on the lowest level of our FPGA-based control hardware during the execution of a circuit. Importantly, this algorithm performs a different randomization per shot with zero runtime overhead beyond measuring a circuit without RC. We implement our algorithm using the QubiC control hardware, where we demonstrate significant reduction in the overall runtime of circuits implemented with RC, as well as a significantly lower variance in measured observables.