A 1.8-um pitch, 47-ps jitter SPAD Array in 130nm SiGe BiCMOS Process

TL;DR

This paper presents the first 130nm SiGe BiCMOS SPAD array with a 1.8um pitch, achieving low jitter and high fill factor, enabling advancements in SWIR and quantum optical applications.

Contribution

It introduces the first SPAD family in 130nm SiGe BiCMOS, demonstrating record small pitch, high fill factor, and scalable array design for SWIR and quantum technologies.

Findings

Smallest pitch on record at 1.8um

Timing jitter of 47 ps FWHM

High fill factor of 24.2%

Abstract

We introduce the world's first SPAD family design in 130 nm SiGe BiCMOS process. At 1.8um, we achieved the smallest pitch on record thanks to guard-ring sharing techniques, while keeping a relatively high fill factor of 24.2%. 4x4 SPAD arrays with two parallel selective readout circuits were designed to explore crosstalk and scalability. The SPAD family has a minimum breakdown voltage of 11 V, a maximum PDP of 40.6% and a typical timing jitter of 47 ps FWHM. The development of silicon SPADs in SiGe process paves the way to Ge-on-Si SPADs for SWIR applications, and to cryogenic optical interfaces for quantum applications.