Demonstration of low power and highly uniform 6-bit operation in SiO2-based memristors embedded with Pt nanoparticles

TL;DR

This paper demonstrates a low-power, highly uniform 6-bit memristor operation using SiO2-based devices with embedded Pt nanoparticles, improving multilevel memory stability and precision.

Contribution

It introduces an optimized fabrication and control scheme for 6-bit memristors with enhanced stability and reliability, advancing high-density, energy-efficient memory technology.

Findings

Enhanced memory window and reduced variability with Pt NPs

Achieved 5-bit precision with ISPP algorithm

Developed a modified scheme for reliable 6-bit operation

Abstract

In this work, an optimized method was implemented for attaining stable multibit operation with low energy consumption in a two-terminal memory element made from the following layers: Ag/Pt nanoparticles (NPs)/SiO2/TiN in a 1-Transistor-1-Memristor configuration. Compared to the reference sample where no NPs were embedded, an enlarged memory window was recorded in conjunction with reduced variability for both switching states. A comprehensive numerical model was also applied to shed light on this enhanced performance, which was attributed to the spatial confinement effect induced by the presence of the Pt NPs and its impact on the properties of the percolating conducting filaments (CFs). Although 5-bit precision was demonstrated with the application of the incremental-step-pulse-programming (ISPP) algorithm, the reset process was unreliable and the output current increased abnormally when exceeded the value of 150 uA. As a result, the multibit operation was limited. To address this issue, a modified scheme was developed to accurately control the distance between the various resistance levels and achieve highly reliable 6-bit precision. Our work provides valuable insights for the development of energy-efficient memories for applications where a high density of conductance levels is required.