Design of Phase Locked Loop in 180 nm Technology
Priyam Kumar, Akshada Khele, Aditee C. Joshi

TL;DR
This paper presents a CMOS PLL design in 180 nm technology capable of generating 2.4 GHz with a wide tuning range, demonstrating effective frequency locking, low power consumption, and fast lock time through simulation and measurement.
Contribution
It introduces a novel 180 nm CMOS PLL design with a 3-stage CSVCO and detailed performance evaluation, including simulation and measurement results.
Findings
Achieves a lock-in range of 70.4 MHz to 173 MHz.
Generates an output frequency from 1.12 GHz to 2.78 GHz.
Consumes a maximum power of 5.15 mW at 2.4 GHz.
Abstract
The presented paper introduces a design for a phase-locked loop (PLL) that is utilized in frequency synthesis and modulation-demodulation within communication systems and in VLSI applications. The CMOS PLL is designed using 180 nm Fabrication Technology on Cadence Virtuoso Tool with a supply voltage of 1.8 V. The performance is evaluated through simulations and measurements, which demonstrate its ability to track and lock onto the input frequency. The PLL is a frequency synthesizer implemented to generate 2.4 GHz frequency. The input reference clock from a crystal oscillator is 150 MHz square wave. Negative feedback is given by divide-by-16 frequency divider, ensuring the phase and frequency synchronization between the divided signal and the reference signal. The design has essential components such as a phase frequency detector, charge pump, loop filter, current-starved…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsVLSI and Analog Circuit Testing · Integrated Circuits and Semiconductor Failure Analysis · Advancements in Semiconductor Devices and Circuit Design
