Performance characterisation of the 64-core SG2042 RISC-V CPU for HPC

TL;DR

This paper evaluates the 64-core SG2042 RISC-V CPU's performance for HPC workloads, showing it outperforms other RISC-V CPUs and performs competitively with x86-64 and AArch64 in compute-bound tasks, but faces memory subsystem bottlenecks.

Contribution

First comprehensive performance characterization of the SG2042 RISC-V CPU for HPC, comparing it with x86-64 and AArch64 architectures using benchmark suites.

Findings

SG2042 outperforms other RISC-V CPUs by 2.6 to 16.7 times in single-core performance.

Performs well on compute-bound algorithms but less so on memory-bound tasks.

Memory subsystem is identified as the main performance bottleneck.

Abstract

Whilst RISC-V has grown phenomenally quickly in embedded computing, it is yet to gain significant traction in High Performance Computing (HPC). However, as we move further into the exascale era, the flexibility offered by RISC-V has the potential to be very beneficial in future supercomputers especially as the community places an increased emphasis on decarbonising its workloads. Sophon's SG2042 is the first mass produced, commodity available, high-core count RISC-V CPU designed for high performance workloads. First released in summer 2023, and at the time of writing now becoming widely available, a key question is whether this is a realistic proposition for HPC applications. In this paper we use NASA's NAS Parallel Benchmark (NPB) suite to characterise performance of the SG2042 against other CPUs implementing the RISC-V, x86-64, and AArch64 ISAs. We find that the SG2042 consistently outperforms all other RISC-V solutions, delivering between a 2.6 and 16.7 performance improvement at the single core level. When compared against the x86-64 and AArch64 CPUs, which are commonplace for high performance workloads, we find that the SG2042 performs comparatively well with computationally bound algorithms but decreases in relative performance when the algorithms are memory bandwidth or latency bound. Based on this work, we identify that performance of the SG2042's memory subsystem is the greatest bottleneck.