Towards the Certification of Hybrid Architectures: Analysing Interference on Hardware Accelerators through PML

TL;DR

This paper explores standards for certifying hybrid hardware platforms with accelerators, analyzing interference issues to ensure safety and compliance in resource-sharing environments.

Contribution

It provides an overview of certification standards applicable to hybrid architectures and maps these standards to various types of accelerators and platforms.

Findings

Analysis of AMC20-152A classification for airborne hardware

Mapping of AMC20-193 standards to multi-core and accelerator platforms

Identification of certification challenges for resource sharing in hybrid systems

Abstract

The emergence of Deep Neural Network (DNN) and machine learning-based applications paved the way for a new generation of hybrid hardware platforms. Hybrid platforms embed several cores and accelerators in a small package. However, in order to satisfy the Size, Weight and Power (SWaP) constraints, limited and shared resources are integrated. This paper presents an overview of the standards applicable to the certification of hybrid platforms and an early mapping of their objectives to said platforms. In particular, we consider how the classification of AMC20-152A for airborne electronic hardware applies to hybrid platforms. We also consider AMC20-193 for multi-core platforms, and how this standard fits different types of accelerators.