Transversal CNOT gate with multi-cycle error correction

TL;DR

This paper demonstrates a scalable method for implementing a transversal CNOT gate with error suppression on logical qubits using quantum error correction, showing feasibility on current IBM quantum hardware.

Contribution

It introduces a transversal CNOT gate between logical qubits with error suppression, using Repetition codes with flag qubits, on real quantum hardware.

Findings

Error suppression improves with larger code sizes.

Logical CNOT gates are feasible on current hardware.

Error detection persists over multiple rounds.

Abstract

A scalable and programmable quantum computer holds the potential to solve computationally intensive tasks that classical computers cannot accomplish within a reasonable time frame, achieving quantum advantage. However, the vulnerability of the current generation of quantum processors to errors poses a significant challenge towards executing complex and deep quantum circuits required for practical problems. Quantum error correction codes such as Stabilizer codes offer a promising path forward for fault-tolerant quantum computing, however their realisation on quantum hardware is an on-going area of research. In particular, fault-tolerant quantum processing must employ logical gates on logical qubits with error suppression with realistically large size codes. This work has implemented a transversal CNOT gate between two logical qubits constructed using the Repetition code with flag qubits, and demonstrated error suppression with increasing code size under multiple rounds of error detection. By performing experiments on IBM quantum devices through cloud access, our results show that despite the potential for error propagation among logical qubits during the transversal CNOT gate operation, increasing the number of physical qubits from 21 to 39 and 57 can suppress errors, which persists over 10 rounds of error detection. Our work establishes the feasibility of employing logical CNOT gates alongside error detection on a superconductor-based processor using current generation quantum hardware.