Quantum Compiling with Reinforcement Learning on a Superconducting Processor

TL;DR

This paper presents a reinforcement learning-based quantum compiler tailored for superconducting quantum processors, capable of generating short, hardware-efficient circuits that improve quantum algorithm implementation on noisy intermediate-scale quantum devices.

Contribution

The study introduces a novel RL-based quantum compiler that discovers hardware-optimized, short quantum circuits, outperforming traditional methods especially under device-specific topological constraints.

Findings

Achieved a 7-CZ gate circuit for three-qubit quantum Fourier transform with perfect fidelity.

Demonstrated shorter circuit lengths compared to conventional compilation methods.

Showcased the compiler's ability to adapt to hardware topological constraints.

Abstract

To effectively implement quantum algorithms on noisy intermediate-scale quantum (NISQ) processors is a central task in modern quantum technology. NISQ processors feature tens to a few hundreds of noisy qubits with limited coherence times and gate operations with errors, so NISQ algorithms naturally require employing circuits of short lengths via quantum compilation. Here, we develop a reinforcement learning (RL)-based quantum compiler for a superconducting processor and demonstrate its capability of discovering novel and hardware-amenable circuits with short lengths. We show that for the three-qubit quantum Fourier transformation, a compiled circuit using only seven CZ gates with unity circuit fidelity can be achieved. The compiler is also able to find optimal circuits under device topological constraints, with lengths considerably shorter than those by the conventional method. Our study exemplifies the codesign of the software with hardware for efficient quantum compilation, offering valuable insights for the advancement of RL-based compilers.